1. Field of the Invention
The invention relates to a class-D amplifier and, more particularly, to a class-D amplifier capable of pushing a two-terminal load in a filterless way.
2. Description of the Prior Art
Compared with the class A amplifier which has low distortion along with high power consumption and the class B amplifier which has low power consumption along with crossover distortion, the class AB amplifier and the class-D amplifier are the in-between amplifier types which can balance the power consumption and the signal quality. Therefore, the class AB and class-D amplifiers are widely applied in audio broadcasters and multimedia players. The main difference between these two types of amplifiers is that, the class AB amplifier utilizes the linear region of the power transistor for amplifying signals, and on the other hand the class-D amplifier operates by the pulse-width modulation (PWM) technology.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram illustrating a half-bridge class-D amplifier 1 in prior art. FIG. 2 is a timing diagram illustrating a signal sampling example of an integration signal Vf, a triangle wave signal VTRI, a PWM signal VPWN in the class-D amplifier 1 in prior art. The class-D amplifier 1 includes an integrator 12, a comparator 14, a driving amplification circuit (including a pre-amp stage 16 and a power amplifier stage 17) and a filter 18. As shown in FIG. 1, one input terminal of integrator 12 is used for receiving an analog signal Vin, and the other input terminal of the integrator 12 is connected to an output node of the power amplifier stage 17 via a resistor R.
The analog signal Vin is integrated by the integrator 12 and transformed into the integration signal Vf. The outcome of the integrator 12 (the integration signal Vf) and a triangle wave signal VTRI are compared by the comparator 14. The triangle wave signal VTRI can serve as the reference for sampling the integration signal Vf. Therefore, the triangle wave signal Vf must have a frequency which is much higher than the frequency of the analog signal Vin, to achieve high quality in sampling.
When the voltage of the integration signal Vf exceeds the voltage of the triangle wave signal VTRI, the outcome of the comparator 14 is a PWM signal VPWN at high level (H); when the voltage of the integration signal Vf is lower than the voltage of the triangle wave signal VTRI, the outcome of the comparator 14 is a PWM signal VPWN at low level (L). The combination of the integrator and the comparator is usually view as the PWM circuit. The origin analog signal can be transformed by the PWM circuit into the digital PWM signal. The amplitude of the origin analog signal is proportional to the high level part out of the digital PWM signal.
Then, the PWM signal VPWN generated by the comparator 14 is further amplified by the pre-amp stage 16, for driving the following power amplifier stage 17, in other words, for controlling the on/off state of the power amplification transistors M1, M2. The power amplifier stage 17 is used for amplifying the power of the output signal. The filter 18, connected with the power amplifier stage 17, includes an inductor L and a capacitor C. The filter 18 is used for filtering out the carrier wave of the PWM signal VPWN and recovering the waveform of the output signal (back to an analog format). The recovered analog signal generated by the class-D amplifier 1 is provided to the load (the speaker 2 in FIG. 1), and it can serve as the driving signal to the speaker 2.
As shown in FIG. 2. When the integration signal Vf is stable at one level (i.e. there is no active input), the PWM signal VPWN has a 50-50 voltage level distribution, 50% at high level and 50% at low level. In this case, one terminal of the speaker 2 is driven by the input signal and the other terminal of the speaker 2 is grounded. In order to prevent the speaker 2 from being damaged by a large direct current (DC), the filter 18 is a must for filtering out the DC part of the PWM signal VPWN. However, in this case, the capacitor of the filter 18 is charged and discharged periodically by the PWM signal VPWN even in a non-active input period.
Although, to implement the filter 18 between the power amplifier stage 17 and the load 2 can be used for filtering out the large DC carrier signal before it reached load 2, but the implementation of the filter may raise production cost, enlarge circuit occupying area, and increase the static power consumption of the class-D amplifier 1.
Please refer to FIG. 3 and FIG. 4. FIG. 3 is a schematic diagram illustrating a circuit structure of a full-bridged class-D amplifier 3 in prior art. FIG. 4 is a timing diagram illustrating a signal sampling example of one set of integration signals (positive integration signal Vf+ and negative integration signal Vf−), a triangle wave signal VTRI, one set of PWM signals (positive PWM signal VPWN+ and negative PWM signal VPWN−) in the class-D amplifier 3 in prior art. In this example, the integrator 32 receives the positive analog signal Vin+ and negative analog signal Vin−, and then outputs the integration outcomes (Vf+, Vf−) to the comparator 34A and the comparator 34B respectively. Afterward, the outputs of the comparators 34A, 34B goes through the process of pre-amp stages (36A, 36B), power amplifier stages (37A, 37B) and filters (38A, 38B), and then the outcomes are used for driving the speaker 4. In this case, the integrator 32 and the comparators 34A, 34B can be views as the PWM circuit.
As shown in FIG. 4. When the integration signals (Vf+, Vf−) is stable at one level (i.e. there is no active input), the PWM signals (VPWN+, VPWN−) has a 50-50 voltage level distribution, which means that the PWM signals has 50% at high level and 50% at low level, and in the mean time the PWM signals are opposed-phased to each other. In this case, the PWM signals are coupled to two terminals of the load 4. In other words, the load 4 is controlled based on the differential portion between the PWM signals (VPWN+, VPWN−). However, while driving the speaker 4 with opposite-phased PWM signals (VPWN+, VPWN−), a large DC signal might be induced to the load 4. Therefore, the class-D amplifier in this embodiment also needs to implement a filter for preventing the speaker 4 from being damaged by a large direct current (DC). In this case, the capacitor of the filter is charged and discharged periodically by the differential portion between the PWM signals (VPWN+, VPWN−) even in a non-active input period. It increases the static power consumption of the class-D amplifier 3.
The invention discloses a class-D amplifier adopting in-phased differential pulse-width modulation, such that the class-D amplifier may drive a load in a filterless way, so as to solve aforesaid problems.